What happened
Published here
On October 2, 2026, researchers Yueting Li and Weihang Ding published SGAnalog, a benchmark built from 273 topologically distinct analog circuit designs drawn from open-source Tiny Tapeout manufacturing shuttles, testing seven models on schematic-to-netlist transcription and device sizing in a fixed containerized pipeline. (SGAnalog paper abstract page on arXiv, submitted October 2, 2026)

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Diagram drawn for this item: Benchmark From Open Chip Tapeouts Shows Claude Models Refusing Sizing Tasks. On October 2, 2026, researchers Yueting Li and Weihang Ding published SGAnalog, a benchmark built from 273 topologically distinct analog circuit designs drawn from open-source Tiny Tapeout manufacturing shuttles, testing seven models on... For a reader weighing which model to trust with a hardware design task, the gap between transcribing a circuit and proposing component values for it is a workflow choice, not just a score: a model that reads a schematic correctly but then...
The numbers
Open-source designs
273
topologically distinct top-level circuit designs in the benchmark
Transcription accuracy
56.1%
strongest model's exact graph isomorphism rate on the transcription task
Sizing score
91.2
leading model's score out of 100 against the human reference on sizing
Refused sizing prompts
11
sizing prompts one of the two newest Claude models refused out of 17
Read from SGAnalog paper abstract page on arXiv, submitted October 2, 2026
What it means for you
For a reader weighing which model to trust with a hardware design task, the gap between transcribing a circuit and proposing component values for it is a workflow choice, not just a score: a model that reads a schematic correctly but then declines to size it leaves the engineer with half a job done and no clear signal why. The paper traces that gap to policy rather than capability in one model family, which means the fix is a prompting or product decision at the vendor, not a training problem the next release will quietly solve.
In more detail
Researchers Yueting Li and Weihang Ding released SGAnalog, a benchmark built entirely from human-designed analog circuits that have already been manufactured through the open-source Tiny Tapeout program. Rather than relying on textbook circuits a model may have memorized during training, the authors pulled 273 topologically distinct designs at the exact revision recorded for each chip’s manufacturing submission, then processed every one through a fixed containerized pipeline that exports both a schematic image and a matching SPICE netlist from the same source file.
The benchmark splits evaluation into two tasks: reading a schematic and turning it into a netlist, and then proposing the component sizes an author’s own testbench would accept. Across seven models tested on 66 transcription tasks, the strongest system reached 56.1 percent exact graph isomorphism, and six of the seven models dropped sharply once circuits moved from the small to the medium size tier. On 17 separate sizing tasks, the leading model converged on proposals for every one and scored 91.2 out of 100 against the human reference.
The detail most relevant to anyone deciding which model to route a hardware task through is what happened with Claude. The two newest Claude models in the test refused 4 and 11 of the same sizing prompts they had transcribed without objection moments earlier. The authors describe this as a policy limit rather than a capability limit in that one model family, since a proposal left blank scores zero regardless of whether the model could have produced sizes.
The numbers
- 273 topologically distinct top-level designs make up the benchmark, each tied to a recorded Tiny Tapeout shuttle submission.
- The strongest model reached 56.1 percent exact graph isomorphism on the 66 transcription tasks, with six of seven models falling off sharply at the medium size tier.
- The leading model converged on all 17 sizing proposals and scored 91.2 out of 100 against the human reference.
- One of the two newest Claude models refused 11 of the 17 sizing prompts it had transcribed without objection.
The authors also tested what happens when author-chosen labels are stripped from a schematic before a frontier model reads it: exact matches fell, but aggregate structural F1 held, suggesting labels help a model trace connectivity rather than recognize the circuit outright. That separation between transcription skill and sizing willingness is the paper’s central finding, and it is the kind of distinction a benchmark built from memorized textbook circuits could not have surfaced.
Sources
Sources read
SGAnalog paper abstract page on arXiv, submitted October 2, 2026 (arxiv.org)
Paper read
Cite this
AI Journey, "Benchmark From Open Chip Tapeouts Shows Claude Models Refusing Sizing Tasks", 7 Oct 2026, https://aijourney.space/updates/2026-10-07-sganalog-an-end-to-end-circuit-benchmark-from-open-source-silicon-tapeou/ (source: arXiv, verified 7 Oct 2026)
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